1. Field of the Invention
This invention relates to an operation execution method and an apparatus employing the operation execution method. This invention has possible applications in pipelined microprocessors, for example.
2. Description of the Prior Art
A single-chip RISC (Reduced Instruction Set Computer) is a device for simultaneously realizing high processing performance, low power consumption, and a small mounting area, primarily in specific applications. Recently, a dedicated arithmetic logic circuit has often been provided in this type of microprocessor to further enhance the arithmetic performance.
One example of this type of microprocessor is the V851 produced by NEC, Ltd. According to NEC Technology Report (Vol. 48, No. 3/1995, pages 42-47), the V851 adopts a pipelined RISC architecture that includes, in addition to an ordinary ALU, a hardware multiplier unit called an MULU for high speed execution of multiplication instructions. A multiplication operation is executed by this multiplier unit in one or two clock cycles.
FIG. 1 shows a state of the pipeline processing by the V851. The figure shows a state where instruction 1 is completed in one clock cycle using the MULU, and subsequent instruction 2 is pipeline processed one clock cycle later. A process corresponding to each clock cycle in the figure is called a stage, and the execution of one instruction is completed after passing through five stages. In the V851, the five stages are called IF, ID, EX, MEM, and WB, where each stage respectively signifies instruction fetch, instruction decode (and register read), operation execution (and memory address generation), memory access (multiplication result fetch), and write back of data for a register file.
In designing a pipelined microprocessor, several different design approaches are available regarding the acceptance of exception processing, such as interrupts. In particular, when providing a dedicated execution circuit such as an arithmetic logic circuit, a design suited for the circuit's characteristics becomes necessary. The major control methods when requests for operation execution and exception processing are generated simultaneously are given below.
(1) Have the exception processing wait
Once the operation has been initiated, the exception processing is made to wait until the execution of the operation completes, and the exception processing is performed after the completion of the operation.
(2) Suspend the operation
The operation is suspended so as to give priority to the exception processing, and the intermediate result of the operation is canceled. After completion of the exception processing, the operation is again performed from the beginning.
(3) Interrupt the operation
The operation is temporarily interrupted, and the intermediate result of the operation is saved. After completion of the exception processing, the saved data is read back and the operation is resumed from the point of interruption.
Among these methods, (1) is the simplest in terms of design and has light hardware requirements, although there is a risk of an urgent exception processing being made to wait for a long period of time, thereby creating a problem in the system. Although method (2) does not have this problem, operations are again executed from the beginning, thereby creating a problem in processing performance. Method (3) does not have these problems, although hardware requirements for implementation increase. For example, in the aforementioned V851, method (1) may be considered practical if an operation requires only a maximum of two clock cycles. However, method (2) or (3) would be the only choices if an execution circuit is provided for floating point arithmetic to handle multi-bit data, for example.